1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) device, and more particularly, to an improvement of the read operation speed of the DRAM.
2. Description of the Related Art
The capacity of semiconductor memory devices has been largely developed. In the past years, the capacity of semiconductor memory devices has increased about four times every three years. At present, 256 Mbit DRAM devices have been disclosed at scientific societies and the like, and samples of 64 Mbit DRAM devices have appeared on the market. Since one memory cell of a DRAM device is constructed by two elements, i.e., one metal oxide semiconductor (MOS) transistor and one capacitor, the DRAM devices are advantageous in respect to the integration as compared with static random access memory (SRAM) devices whose memory cell is constructed by six elements. The DRAM devices of one generation have four times the capacity of SRAM devices of the same generation. That is, there is a large difference in capacity between the DRAM devices and the SRAM devices.
On the other hand, the SRAM devices have an advantage in that operation speed is very high. For example, the operation speed time of a 16 Mbit DRAM device is about 60 ns due to its synchronous operation, while that of a 4 Mbit SRAM device is about 20 ns due to its asynchronous operation. However, the asynchronous operation of DRAM devices is not essential. Actually, some DRAM devices can be operated asynchronously in a special mode such as a static column operation mode, and in this case, the operation speed is about 20 ns, the same as in the SRAM devices.
The low operation speed of the DRAM devices is due to the read operation thereof. That is, in a prior art DRAM device including a plurality of word lines, a plurality of bit lines and a plurality of dynamic memory cells connected to the word lines and the bit lines, one pair of the bit lines are connected to one sense amplifier which is connected by a switching circuit to a read amplifier. Therefore, after the sense amplifier is operated to enter a refresh mode, the read amplifier is connected by the switching circuit to the read amplifier to enter a read mode. As a result, the read operation speed is reduced. This will be explained later in detail.